// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  ring_cfg_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  Huawei
// Version       :  1.0
// Date          :  2017/11/13
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/03/19 15:43:14 Create file
// ******************************************************************************

#ifndef __RING_CFG_REG_OFFSET_FIELD_H__
#define __RING_CFG_REG_OFFSET_FIELD_H__

#define RING_CFG_SRST_REQ_HW_AIC1_LEN    1
#define RING_CFG_SRST_REQ_HW_AIC1_OFFSET 1
#define RING_CFG_SRST_REQ_HW_AIC0_LEN    1
#define RING_CFG_SRST_REQ_HW_AIC0_OFFSET 0

#define RING_CFG_SRST_DREQ_HW_AIC1_LEN    1
#define RING_CFG_SRST_DREQ_HW_AIC1_OFFSET 1
#define RING_CFG_SRST_DREQ_HW_AIC0_LEN    1
#define RING_CFG_SRST_DREQ_HW_AIC0_OFFSET 0

#define RING_CFG_SYS_MBIST_CLKEN_DATA_LEN    2
#define RING_CFG_SYS_MBIST_CLKEN_DATA_OFFSET 2
#define RING_CFG_SYS_MBIST_CLKEN_TAG_LEN     1
#define RING_CFG_SYS_MBIST_CLKEN_TAG_OFFSET  1
#define RING_CFG_SYS_MBIST_CLKMUX_LEN        1
#define RING_CFG_SYS_MBIST_CLKMUX_OFFSET     0

#define RING_CFG_CLOSE_PORT14_LEN    1
#define RING_CFG_CLOSE_PORT14_OFFSET 14
#define RING_CFG_CLOSE_PORT13_LEN    1
#define RING_CFG_CLOSE_PORT13_OFFSET 13
#define RING_CFG_CLOSE_PORT12_LEN    1
#define RING_CFG_CLOSE_PORT12_OFFSET 12
#define RING_CFG_CLOSE_PORT11_LEN    1
#define RING_CFG_CLOSE_PORT11_OFFSET 11
#define RING_CFG_CLOSE_PORT10_LEN    1
#define RING_CFG_CLOSE_PORT10_OFFSET 10
#define RING_CFG_CLOSE_PORT9_LEN     1
#define RING_CFG_CLOSE_PORT9_OFFSET  9
#define RING_CFG_CLOSE_PORT6_LEN     1
#define RING_CFG_CLOSE_PORT6_OFFSET  6
#define RING_CFG_CLOSE_PORT3_LEN     1
#define RING_CFG_CLOSE_PORT3_OFFSET  3
#define RING_CFG_CLOSE_PORT2_LEN     1
#define RING_CFG_CLOSE_PORT2_OFFSET  2
#define RING_CFG_CLOSE_PORT1_LEN     1
#define RING_CFG_CLOSE_PORT1_OFFSET  1
#define RING_CFG_CLOSE_PORT0_LEN     1
#define RING_CFG_CLOSE_PORT0_OFFSET  0

#define RING_CFG_LINKDOWN_REQ_AICORE1_LEN    1
#define RING_CFG_LINKDOWN_REQ_AICORE1_OFFSET 1
#define RING_CFG_LINKDOWN_REQ_AICORE0_LEN    1
#define RING_CFG_LINKDOWN_REQ_AICORE0_OFFSET 0

#define RING_CFG_SD_MODE_AICORE_LEN    1
#define RING_CFG_SD_MODE_AICORE_OFFSET 0

#define RING_CFG_MEM_POWER_MODE_SD_SMMU1_LEN    1
#define RING_CFG_MEM_POWER_MODE_SD_SMMU1_OFFSET 3
#define RING_CFG_MEM_POWER_MODE_SD_AIC1_LEN     1
#define RING_CFG_MEM_POWER_MODE_SD_AIC1_OFFSET  2
#define RING_CFG_MEM_POWER_MODE_SD_SMMU0_LEN    1
#define RING_CFG_MEM_POWER_MODE_SD_SMMU0_OFFSET 1
#define RING_CFG_MEM_POWER_MODE_SD_AIC0_LEN     1
#define RING_CFG_MEM_POWER_MODE_SD_AIC0_OFFSET  0

#define RING_CFG_SRST_ST_HW_AIC1_LEN    1
#define RING_CFG_SRST_ST_HW_AIC1_OFFSET 1
#define RING_CFG_SRST_ST_HW_AIC0_LEN    1
#define RING_CFG_SRST_ST_HW_AIC0_OFFSET 0

#define RING_CFG_PERI_CFG_VERSION0_LEN    32
#define RING_CFG_PERI_CFG_VERSION0_OFFSET 0

#define RING_CFG_LINKDOWN_ACK_AICORE1_LEN    1
#define RING_CFG_LINKDOWN_ACK_AICORE1_OFFSET 1
#define RING_CFG_LINKDOWN_ACK_AICORE0_LEN    1
#define RING_CFG_LINKDOWN_ACK_AICORE0_OFFSET 0

#define RING_CFG_PERI_CFG_MAGIC_WORD_LEN    32
#define RING_CFG_PERI_CFG_MAGIC_WORD_OFFSET 0

#define RING_CFG_SYSCTRL_LOCK_LEN    32
#define RING_CFG_SYSCTRL_LOCK_OFFSET 0

#define RING_CFG_SYSCTRL_UNLOCK_LEN    32
#define RING_CFG_SYSCTRL_UNLOCK_OFFSET 0

#define RING_CFG_ECO_RSV0_LEN    32
#define RING_CFG_ECO_RSV0_OFFSET 0

#define RING_CFG_ECO_RSV1_LEN    32
#define RING_CFG_ECO_RSV1_OFFSET 0

#define RING_CFG_ECO_RSV2_LEN    32
#define RING_CFG_ECO_RSV2_OFFSET 0

#define RING_CFG_ECO_RSV3_LEN    32
#define RING_CFG_ECO_RSV3_OFFSET 0

#define RING_CFG_PROTOTYPE_CLK_LEN    32
#define RING_CFG_PROTOTYPE_CLK_OFFSET 0

#define RING_CFG_PROTOTYPE_RST_N_LEN    32
#define RING_CFG_PROTOTYPE_RST_N_OFFSET 0

#define RING_CFG_FPGA_VERI_NUM_LEN    32
#define RING_CFG_FPGA_VERI_NUM_OFFSET 0

#endif // __RING_CFG_REG_OFFSET_FIELD_H__
